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CPU ID - Cache configuration registers
CPUID Results (EAX = 2) Get Cache Configuration Descriptors
[CPUID instruction only available if ID Flag of EFLAGS register can be toggled]
[Function 2 only valid if previous call to CPUID with Function 0 returned EAX >= 2]
EAX, EBX, ECX, EDX = Cache Descriptors (8 bits each, packed end to end)
The lowest 8 bits of EAX (AL) contain the values 00000001, other values are reserved for future use. The remainder
of EAX as well as EBX, ECX, and EDX all contain valid 8 bit descriptors. Valid descriptors may be identified because
the most significant bit of the 8 bit descriptor is set to 0. The following is a list of current descriptor values
and their respective cache characteristics:
| Descriptor value |
Description |
| 00000000 |
unused (NULL descriptor) |
| 00000001 |
code TLB, 4K pages, 4-way set associative, 64 entries |
| 00000010 |
code TLB, 4M pages, 4-way set associative, 4 entries |
| 00000011 |
data TLB, 4K pages, 4-way set associative, 64 entries |
| 00000100 |
data TLB, 4M pages, 4-way set associative, 8 entries |
| 00000110 |
instruction cache, 8K, 4-way set associative, 32-byte lines |
| 00001100 |
data cache, 8K, 4-way set associative, 32-byte lines |
| 00000001 |
code/data cache, 128K, 4-way set associative, 32-byte lines |
| 01000010 |
code/data cache, 256K, 4-way set associative, 32-byte lines |
| 01000011 |
code/data cache, 512K, 4-way set associative, 32-byte lines |
| CR0 (Control Register) |
| Bit name |
Description |
| 0 Protection Enable |
(1) Processor is in protected mode
(0) Processor is in real mode |
| 1 Math Present |
(1) The WAIT instruction will raise a 'Device Not Available'
exception is the Task Switched flag is set.
(0) The WAIT instruction operates as normal. |
| 2 Emulate |
(1) Floating point instructions will raise a 'Device Not
Available' exception.
(0) Floating point instructions will be sent directly to the processor.
Note: The WAIT instruction ignores the setting of this bit and is
controlled solely by the Math Present bit. |
| 3 Task Switched |
Set whenever a task switch occurs. While set, any floating
point instruction will generate an exception before it is executed. A WAIT
instruction will generate an exception also only if the Math Present bit
is also set. |
| 4 Extension Type |
(1) Math Coprocessor is a 387 or later part (32-bit)
(0) Math Coprocessor is a 287 part ( 16-bit) or is not present.
Note: this bit is set by the processor whenever it is reset and should
not be changed by software. |
| 5 (undefined) |
Always set to 0 |
| 6 (undefined) |
Always set to 0 |
| 7 (undefined) |
Always set to 0 |
| 8 (undefined) |
Always set to 0 |
| 9 (undefined) |
Always set to 0 |
| 10 (undefined) |
Always set to 0 |
| 11 (undefined) |
Always set to 0 |
| 12 (undefined) |
Always set to 0 |
| 13 (undefined) |
Always set to 0 |
| 14 (undefined) |
Always set to 0 |
| 15 (undefined) |
Always set to 0 |
| 20 (undefined) |
Always set to 0 |
| 21 (undefined) |
Always set to 0 |
| 22 (undefined) |
Always set to 0 |
| 23 (undefined) |
Always set to 0 |
| 24 (undefined) |
Always set to 0 |
| 25 (undefined) |
Always set to 0 |
| 26 (undefined) |
Always set to 0 |
| 27 (undefined) |
Always set to 0 |
| 28 (undefined) |
Always set to 0 |
| 29 (undefined) |
Always set to 0 |
| 30 (undefined) |
Always set to 0 |
| 31 Paging Enable |
(1) Linear addresses are translated to physical addresses
by the processor's paging mechanism.
(0) Linear addresses are directly mapped to physical addresses. |
| CR2 (Control Register) |
| Used to report linear address which caused paging exception. |
| CR3 (Control Register) |
| Bit name |
Description |
| 0 (undefined) |
Always set to 0 |
| 1 (undefined) |
Always set to 0 |
| 2 (undefined) |
Always set to 0 |
| 3 Page Write Through |
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| 4 Page Cache Disable |
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| 5 (undefined) |
Always set to 0 |
| 6 (undefined) |
Always set to 0 |
| 7 (undefined) |
Always set to 0 |
| 8 (undefined) |
Always set to 0 |
| 9 (undefined) |
Always set to 0 |
| 10 (undefined) |
Always set to 0 |
| 11 (undefined) |
Always set to 0 |
| 12 Page Directory Base |
Page (4K) granular physical address of the Page Directory,
The Page Directory controls the entire paging mechanism for the translation
of linear addresses to physical addresses. |
| 13 |
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| 14 |
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| 15 |
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| 16 |
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| 17 |
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| 18 |
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| 19 |
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| 20 |
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| 21 |
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| 22 |
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| 23 |
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| 24 |
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| 25 |
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| 26 |
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| 27 |
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| 28 |
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| 29 |
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| 30 |
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| 31 |
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| CR4 (Control Register) |
| Bit name |
Description |
| 0 Virtual Mode Extensions |
(1) Virtual8086 Mode Extensions are enabled. See description
of Virtual8086 Mode Extensions for details.
(0) Virtual8086 Mode behaves as defined for a 80386. |
| 1 Virtual Interrupts |
(1) Protected Mode Virtual Interrupts are enabled. While
this bit is set and the task's current privilege level is outside the task's
I/O privilege level and instructions which modify the Interrupt Flag actually
modify the Virtual Interrupt Flag.
(0) Protected Mode interrupts are not virtualized and therefore do actually
modify the Interrupt Flag. |
| 2 Time Stamp Disable |
(1) Read Time Stamp Counter instruction is a privileged
instruction that may only be executed if current privilege level is 0 without
causing a protection fault.
(0) Read Time Stamp Counter instruction is not a privileged instruction
and therefore can be executed at any privilege level. |
| 3 Debugging Extensions |
(1) Debugging Extensions are enabled. I/O breakpoints
may be defined and Debug Registers 4 and 5 are protected. See description
of Debug Registers for details.
(0) Debugging Extensions are disabled. Processor-level debug support behaves
as defined for a 80386; Debug Registers 4 and 5 are aliases of Debug Registers
6 and 7 respectively and I/O breakpoints cannot be set. |
| 4 Page Size Extension |
(1) The Page Size Extension is enabled. If the Page Size
flag of a Page Directory Entry is set then the entry describes a 4M page.
If the Page Size flag of a Page Directory Entry is clear then the entry
is a table of up to 1024 Page Table Entries each of which describing a 4K
page.
(0) The Page Size Extension is disabled and Page lookups are performed as
defined for a 80386. Setting the Page Size flag of a Page Directory generates
a protection fault. |
| 5 Physical Address Extension |
(1) Processor support for 36-bit physical address space
and related paging mechanisms are enabled. See description of Page Address
Extensions for details.
(0) Processor can only access 32 bits of address space as defined for a
80386. |
| 6 Machine Check Exception |
(1) A Machine Check Exception is generated whenever a
fatal system error is detected such as failed memory parity check.
(0) No exception is generated. |
| 7 Page Global Extensions |
(1) Reloading CR3 (the Page Directory Base) clears all
entries from the Translation Look-aside Buffer, the processor's internal
caching mechanism for Page Table Entries, except for Page Eable Entries
or Page Directory Entries with the Global flag set.
(0) Reloading CR3 clears all entries from the Translation Look-aside Buffer
as defined for a 80386. |
| 8 Performance Counter |
(1) Read Performance Counter instruction is a privileged
instruction that may only be executed if current privilege level is 0 without
causing a protection fault.
(0) Read Performance Counter instruction is not a privileged instruction
and therefore can be executed at any privilege level. |
| 9 (undefined) |
Always set to 0 |
| 10 (undefined) |
Always set to 0 |
| 11 (undefined) |
Always set to 0 |
| 12 (undefined) |
Page (4K) granular physical address of the Page Directory,
The Page Directory controls the entire paging mechanism for the translation
of linear addresses to physical addresses. |
| 13 (undefined) |
Always set to 0 |
| 14 (undefined) |
Always set to 0 |
| 15 (undefined) |
Always set to 0 |
| 16 (undefined) |
Always set to 0 |
| 17 (undefined) |
Always set to 0 |
| 18 (undefined) |
Always set to 0 |
| 19 (undefined) |
Always set to 0 |
| 20 (undefined) |
Always set to 0 |
| 21 (undefined) |
Always set to 0 |
| 22 (undefined) |
Always set to 0 |
| 23 (undefined) |
Always set to 0 |
| 24 (undefined) |
Always set to 0 |
| 25 (undefined) |
Always set to 0 |
| 26 (undefined) |
Always set to 0 |
| 27 (undefined) |
Always set to 0 |
| 28 (undefined) |
Always set to 0 |
| 29 (undefined) |
Always set to 0 |
| 30 (undefined) |
Always set to 0 |
| 31 (undefined) |
Always set to 0 |
| DR0-3 (Debug Breakpoint Registers) |
| Contain the linear address associated
with each of the four breakpoint conditions. Additional breakpoint qualifiers
are located in DR7. |
| DR6 (Debug Status Register) |
| The processor never clears any bits in register
DR6. If DR7 indicates that an exception should be generated for a given
condition, the handler has the responsibility to clear DR6 before terminating
so that future exceptions can properly detect the cause. In addition it
should be noted that the breakpoint detected flags will be set whether an
exception is generated for the condition or not; it is then also the responsibility
of the debug exception handler to ignore any breakpoint detected flags coresponding
to breakpoints not specifically enabled by DR7. (The same is true for the
Debug Protection flag) |
| Bit name |
Description |
| 0 Breakpoint (0) Detected |
(1) Processor sets this bit to indicate
that the breakpoint condition specified by breakpoint linear address register
DR0 was detected.
Note: This bit is set even if the breakpoint condition has not been
specifically enabled by DR7
(0) The breakpoint condition indicated by DR0 has not been detected. |
| 1 Breakpoint (1) Detected |
(1) Processor sets this bit to indicate
that the breakpoint condition specified by breakpoint linear address register
DR1 was detected.
Note: This bit is set even if the breakpoint condition has not been
specifically enabled by DR7
(0) The breakpoint condition indicated by DR1 has not been detected. |
| 2 Breakpoint (2) Detected |
(1) Processor sets this bit to indicate
that the breakpoint condition specified by breakpoint linear address register
DR2 was detected.
Note: This bit is set even if the breakpoint condition has not been
specifically enabled by DR7
(0) The breakpoint condition indicated by DR2 has not been detected. |
| 3 Breakpoint (3) Detected |
(1) Processor sets this bit to indicate
that the breakpoint condition specified by breakpoint linear address register
DR3 was detected.
Note: This bit is set even if the breakpoint condition has not been
specifically enabled by DR7
(0) The breakpoint condition indicated by DR3 has not been detected. |
| 4 (undefined) |
Always set to 0 |
| 5 (undefined) |
Always set to 0 |
| 6 (undefined) |
Always set to 0 |
| 7 (undefined) |
(Always set to 0 |
| 8 (undefined) |
Always set to 0 |
| 9 (undefined) |
Always set to 0 |
| 10 (undefined) |
Always set to 0 |
| 11 (undefined) |
Always set to 0 |
| 12 (undefined) |
Always set to 0 |
| 13 Debug Protection |
(1) Processor sets this bit to indicate
that the next instruction to be executed will read or write to a debug register.
Note: This bit is set even if Debug Protection is not enabled in
DR7
(0) Next instruction does not attempt to modify a debug register. |
| 14 Single Step |
(1) Processor sets this bit if the program
enters the debug exception handler because of a single-step condition. The
single-step condition is enabled by the Trap Flag bit in the EFLAGS register.
(0) Debug exception was not triggered by a single-step trap. |
| 15 Task Switch Breakpoint |
(1) Processor sets this bit if the program
enters the debug exception handler because a task switched occurred to a
task with the Debug Trap bit in its TSS enabled.
(0) Debug exception was not triggered by a task switch to a task with its
Debug Trap bit enabled. |
| 16 (undefined) |
Always set to 0 |
| 17 (undefined) |
Always set to 0 |
| 18 (undefined) |
Always set to 0 |
| 19 (undefined) |
Always set to 0 |
| 20 (undefined) |
Always set to 0 |
| 21 (undefined) |
Always set to 0 |
| 22 (undefined) |
Always set to 0 |
| 23 (undefined) |
Always set to 0 |
| 24 (undefined) |
Always set to 0 |
| 25 (undefined) |
Always set to 0 |
| 26 (undefined) |
Always set to 0 |
| 27 (undefined) |
Always set to 0 |
| 28 (undefined) |
Always set to 0 |
| 29 (undefined) |
Always set to 0 |
| 30 (undefined) |
Always set to 0 |
| 31 (undefined) |
Always set to 0 |
| DR7 (Debug Status Register) |
| Bit name |
Description |
| 0 Local Breakpoint (0) |
Always set to 0 |
| 1 Global Breakpoint (0) |
Always set to 0 |
| 2 Local Breakpoint (1) |
Always set to 0 |
| 3 Global Breakpoint (1) |
Always set to 0 |
| 0 Local Breakpoint (2) |
Always set to 0 |
| 5 Global Breakpoint (2) |
Always set to 0 |
| 0 Local Breakpoint (3) |
Always set to 0 |
| 7 Global Breakpoint (3) |
Always set to 0 |
| 0 Local Breakpoint Enable |
(1) Processor will slow execution such
that data breakpoints are reported on exactly the instruction which causes
them.
(0) Processor will run at full speed and may get slightly ahead of the reporting
of the breakpoint conditions on instructions that perform data writes near
the end of their execution.
Note: The processor automatically clears this flag whenever a task
switch occurs. |
| 7 Global Breakpoint Enable |
(1) Processor will slow execution such
that data breakpoints are reported on exactly the instruction which causes
them.
(0) Processor will run at full speed and may get slightly ahead of the reporting
of the breakpoint conditions on instructions that perform data writes near
the end of their execution. |
| 10 (undefined) |
Always set to 0 |
| 11 (undefined) |
Always set to 0 |
| 12 (undefined) |
Always set to 0 |
| 13 Debug Protection Enable |
(1) Enables the debug register protection
condition which is reported by the Debug Protection bit of DR6. Any attempt
to modify the debug registers will generate a debug exception which can
be detected by testing the Debug Protection bit of DR6.
(0) Disables the debug register protection condition. Software may freely
modify the state of any of the debug registers.
Note: The processor automatically clears this flag on entry to the
debug exception handler allowing it free access to the debug registers. |
| 14 (undefined) |
Always set to 0 |
| 15 (undefined) |
Always set to 0 |
| 16-17 Breakpoint (0) Condition |
Condition which triggers breakpoint
0. If either the Local Breakpoint(0) or the Global Breakpoint(0) bits are
set then an exception will be generated whenever this condition is met.
Values for breakpoint conditions are:
00 = Instruction execution only
01 = Data writes only
10 = If Debugging Extensions are enabled in CR4, I/O reads and writes;
If Debugging Extensions are disabled or not supported, undefined.
11 = Data reads and writes |
| 18-19 Breakpoint (0) Length |
Always set to 0 |
| 20-21 Breakpoint (1) Condition |
Always set to 0 |
| 22-23 Breakpoint (1) Length |
Always set to 0 |
| 24-25 Breakpoint (2) Condition |
Always set to 0 |
| 26-27 Breakpoint (2) Length |
Always set to 0 |
| 28-29 Breakpoint (3) Condition |
Always set to 0 |
| 30-31 Breakpoint (3) Length |
Always set to 0 |
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