| Bit |
Flag name |
Description |
| 00 |
Carry Flag |
Set when an arithmetic
operation generates a carry or a borrow. Provides an overflow indication
for unsigned arithmetic. |
| 01 |
undefined |
Always set to 1 |
| 02 |
Parity Flag |
Set when the parity of
the lower 8 bits of the result is even. |
| 03 |
undefined |
Always set to 0 |
| 04 |
Auxiliary Flag |
Set when an arithmetic
operation generates a carry or a borrow out of bit 3. This is used in performing
Binary Coded Decimal operations. |
| 05 |
undefined |
Always set to 0 |
| 06 |
Zero Flag |
Set when the result of
an operation is 0. |
| 07 |
Sign Flag |
Set to the most significant
bit of the result of an operation. The most significant bit is the sign
bit in two's complement notation. |
| 08 |
Trap Flag |
(1) A single-step interrupt
will occur after every instruction.
(0) Normal instruction execution
(!) Trap Flag is always cleared when an interrupt is generated either by
software or hardware. |
| 09 |
Interrupt Flag |
(1) Enables the recognition
of external interrupts.
(0) External interrupts are held pending. |
| 10 |
Direction Flag |
(1) String instructions
post-decrement the string index register after each step.
(0) String instructions post-increment the string index register after each
step. |
| 11 |
Overflow Flag |
Set if the result of an
arithmetic operation is too large or too small to be represented as a two's
complement integer in the number of bits available to store the result |
| 12 |
I/O Privilege
Level |
Supports protection
model. Indicates the privilege level required to perform I/O instructions.
If the current privilege level is numerically less than or equal to the
IOPL, I/O intructions can be executed. |
| 13 |
| 14 |
Nested Task Flag |
(1) Controls operation
of IRET instruction. The IRET (interrupt return) instruction will return
through a task switch to the task indicated in the current TSS.
(0) A normal return is performed by restoring EFLAGS, CS and EIP with values
from the stack |
| 15 |
undefined |
Always set to 0 |
| 16 |
Restart Flag |
(1) Indicates that debug
faults should be ignored.
(0) Debug faults are accepted.
(!) This bit is cleared by the processor at the successful completion of
every instruction, and is set when a fault other than a debug fault is signalled. |
| 17 |
Virtual Mode Flag |
(1) Processor will execute
this task in Virtual 8086 mode.
(0) Processor will execute this task in normal protected mode. |
| 18 |
Alignment Check |
(1) Processor will generate
an Alignment Check Fault whenever a memory reference is made from privilege
level 3 to a misaligned address. A misaligned address is defined as any
data reference that is not evenly divisible by its size.
(0) Processor operates normal; it does not generate faults on misaligned
addresses.
(!) 486 and higher only |
| 19 |
Virtual Interrupt Flag |
(1) Virtualizes Interrupt
flag when Virtual 8086 Mode Extensions or Protected Mode Extensions are
enabled. When set indicates that interrupts are handled as usual.
(0) Indicates that current task should not receive external interrupts.
If an interrupt is generated while this flag is clear then a protected mode
exception is generated.
(!) Virtual or Protected Mode Extensions Supported Only |
| 20 |
Virtual Interrupt Pending |
This bit is used by the
operating system to indicate to the processor that a virtualized interrupt
is pending for the current task. If set, then any attempt to toggle the
Virtual Interrupt Flag to the on state will generate a protected mode exception.
(!) Virtual or Protected Mode Extensions Supported Only |
| 21 |
ID Flag |
If this bit can be toggled
then the processor supports the CPUID instruction. |
| 22 |
undefined |
Always set to 0 |
| 23 |
undefined |
Always set to 0 |
| 24 |
undefined |
Always set to 0 |
| 25 |
undefined |
Always set to 0 |
| 26 |
undefined |
Always set to 0 |
| 27 |
undefined |
Always set to 0 |
| 28 |
undefined |
Always set to 0 |
| 29 |
undefined |
Always set to 0 |
| 30 |
undefined |
Always set to 0 |
| 31 |
undefined |
Always set to 0 |
