| Bit |
Flag name |
Description |
| 00 |
FPU |
(1) Processor contains a built-in FPU which supports the i387 instruction set.
(0) Processor does not contain an on-chip FPU supporting the i387 instruction
set, although a math coprocessor may be present. |
| 01 |
Virtual Mode Enhancements |
(1) Virtual Mode Enhancements are supported and may be toggled via bit 0 in Control Register 4.
(0) Virtual Mode Enhancements are not supported. |
| 02 |
Debugging Extensions |
(1) Debugging Extensions are supported and may be toggled via bit 3 in Control Register 4.
(0) Debugging Extensions are not supported. |
| 03 |
Page Size Extension |
(1) The Page Size Extension is supported and may be toggled via bit 4 in Control Register 4.
(0) The Page Size Extension is not supported. |
| 04 |
Time Stamp Counter |
(1) The RDTSC (Read Time Stamp Counter) instruction is supported and access may be controlled via
bit 2 in Control Register 4.
(0) The RDTSC (Read Time Stamp Counter) instruction is not supported. |
| 05 |
Model Specific Registers |
(1) Model Specific Registers are implemented
with RDMSR (Read Model Specific Register) and WRMSR (Write Model Specific Register) instructions.
(0) Model Specific Registers are not supported. |
| 06 |
Physical Address Extension |
(1) Physical Addresses larger than 32-bit are supported.
(0) Physical Addresses are limited to 32 bits. |
| 07 |
Machine Check Exception |
(1) Machine Check Exception (#12h) is supported
and may be enabled or disabled by toggling bit 6 of Control Register 4.
(0) Machine Check Exception (#12h) is not supported. |
| 08 |
Compare and Exchange |
(1) The CMPXCHG8 (Compare and exchange 8 bytes) instruction is supported.
(0) The CMPXCHG8 (Compare and exchange 8 bytes) instruction is not supported. |
| 09 |
Local APIC |
(1) The processor contains a local APIC (Advanced Programmable Interrupt Controller)
(0) The processor does not contain a local APIC, instead relying on an external
Programmable Interrupt Controller. |
| 10 |
reserved |
|
| 11 |
reserved |
|
| 12 |
Memory Type Range |
(1) Memory Type Range Registers supported.
(0) Memory Type Range Registers are not supported. |
| 13 |
Page Global Enable |
(1) Page Global Enable supported.
(0) Page Global Enable not supported. |
| 14 |
Machine Check Architecture |
|
| 15 |
Conditional Move |
(1) Conditional Move instructions (CMOVxx, FCMOVxx, and FCOMI) are supported.
(0) Conditional Move instructions are not supported. |
| 16 |
reserved |
|
| 17 |
reserved |
|
| 18 |
reserved |
|
| 19 |
reserved |
|
| 20 |
reserved |
|
| 21 |
reserved |
|
| 22 |
reserved |
|
| 23 |
MMX |
(1) 'Multimedia' instruction set supported.
(0) 'Multimedia' instruction set not supported. |
| 24 |
reserved |
|
| 25 |
reserved |
|
| 26 |
reserved |
|
| 27 |
reserved |
|
| 28 |
reserved |
|
| 29 |
reserved |
|
| 30 |
reserved |
|
| 31 |
reserved |
|
