ISA bus family

VLB (VESA local bus)

VESA Local Bus was developed by several mainboard manufacturers with a major focus on low implementation costs. As a result extensions like bridges or buffers weren't used. With version 1.0 of VLB specifications weren't very tight and manufacturers had much freedom for interpretation.
VLB is directly connected to the CPU bus which ran at a maximum of 40MHz at time of specification. So VLB was specified for a maximum of 40MHz too. With later CPU's like intel 486DX50 a FSB of 50MHz and higher was introduced and manufacturers of expansion cards specified their cards for different bus layouts.
No mainboards carries an identification for VLB specification implemented nor have expansion cards this printed on. This results in many incompatibilities mostly caused by overclocking cards that were only tested with FSB up to 40MHz.

As no buffers were defined in the design of VLB the number of usable VLB slots depends on the FSB:
FSB VLB slots (v1.0) VLB slots (v2.0) VLB slots (64)
25 MHz 3 3 3
33 MHz 3 3 3
40 MHz 1 2..3 2..3
50 MHz   1..2 1..2
60MHz   1 1

VLB information:
Bus width 32 Bit
Bus clock 25 bis 66 MHz
Max bandwidth 40..80 MB/s
Max slots see above

Effective bandwith
33MHz w/o Extra-Wait
Non-Burst-Read 33 MB/s
Non-Burst-Write 44 MB/s
Burst-Read 53,8 MB/s
Burst-Write 75,4 MB/s
40 MHz w/o Extra-Wait
Non-Burst-Read 40 MB/s
Non-Burst-Write 40 MB/s
Burst-Read 64 MB/s
Burst-Write 64 MB/s
50MHz w/o Extra-Wait
Non-Burst-Read 50 MB/s
Non-Burst-Write 50 MB/s
Burst-Read 80 MB/s
Burst-Write 80 MB/s

OPTi local bus